1 #ifndef LIBRARIES_OPENPCI_H 2 #define LIBRARIES_OPENPCI_H 3 4 /* 5 ** $VER: openpci.h 1.4 (27.09.2002) 6 ** Includes Release 1.4 7 ** 8 ** openpci.library interface structures and definitions. 9 ** 10 */ 11 12 /*****************************************************************************/ 13 14 15 #ifndef EXEC_TYPES_H 16 #include <exec/types.h> 17 #endif 18 19 #ifndef HARDWARE_BYTESWAP_H 20 #include <hardware/byteswap.h> 21 #endif 22 23 #pragma pack(2) 24 25 #define MIN_OPENPCI_VERSION 2 /* Version 2 or more */ 26 27 /* pci_bus() result flags */ 28 #define MediatorA1200Bus 0x1 29 #define MediatorZ4Bus 0x2 30 #define PrometheusBus 0x4 31 #define GrexA1200Bus 0x8 32 #define GrexA4000Bus 0x10 33 #define PegasosBus 0x20 34 #define PowerPciBus 0x40 35 36 /* pci_allocdma_mem flags */ 37 #define MEM_PCI 0x1 38 #define MEM_NONCACHEABLE 0x2 39 40 /*****************************************************************************/ 41 42 struct pci_dev { 43 struct pci_bus *bus; /* bus this device is on */ 44 struct pci_dev *next; /* Next pci_dev */ 45 struct pci_dev *pred; /* Previous pci_dev */ 46 47 unsigned char devfn; /* encoded device & function index */ 48 unsigned short vendor; 49 unsigned short device; 50 unsigned int devclass; /* 3 bytes: (base,sub,prog-if) */ 51 unsigned int hdr_type; /* PCI header type */ 52 unsigned int master : 1; /* set if device is master capable */ 53 /* 54 * In theory, the irq level can be read from configuration 55 * space and all would be fine. However, old PCI chips don't 56 * support these registers and return 0 instead. For example, 57 * the Vision864-P rev 0 chip can uses INTA, but returns 0 in 58 * the interrupt line and pin registers. pci_init() 59 * initializes this field with the value at PCI_INTERRUPT_LINE 60 * and it is the job of pcibios_fixup() to change it if 61 * necessary. The field must not be 0 unless the device 62 * cannot generate interrupts at all. 63 */ 64 unsigned int irq; /* irq generated by this device */ 65 66 /* Base registers for this device, can be adjusted by 67 * pcibios_fixup() as necessary. 68 */ 69 unsigned long base_address[6]; 70 unsigned long base_size[6]; 71 unsigned long rom_address; 72 unsigned long rom_size; 73 74 void *reserved; 75 }; 76 77 struct pci_bus { 78 struct pci_bus *parent; /* parent bus this bridge is on */ 79 struct pci_bus *children; /* chain of P2P bridges on this bus */ 80 struct pci_bus *next; /* chain of all PCI buses */ 81 82 struct pci_dev *self; /* bridge device as seen by parent */ 83 struct pci_dev *devices; /* devices behind this bridge */ 84 85 unsigned char number; /* bus number */ 86 unsigned char primary; /* number of primary bridge */ 87 unsigned char secondary; /* number of secondary bridge */ 88 unsigned char subordinate; /* max number of subordinate buses */ 89 }; 90 91 /* 92 * Under PCI, each device has 256 bytes of configuration address space, 93 * of which the first 64 bytes are standardized as follows: 94 */ 95 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 96 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 97 #define PCI_COMMAND 0x04 /* 16 bits */ 98 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 99 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 100 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 101 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 102 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 103 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 104 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 105 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 106 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 107 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 108 109 #define PCI_STATUS 0x06 /* 16 bits */ 110 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 111 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features */ 112 113 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 114 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 115 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 116 #define PCI_STATUS_DEVSEL_FAST 0x000 117 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 118 #define PCI_STATUS_DEVSEL_SLOW 0x400 119 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 120 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 121 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 122 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 123 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 124 125 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 126 revision */ 127 #define PCI_REVISION_ID 0x08 /* Revision ID */ 128 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 129 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 130 131 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 132 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 133 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 134 #define PCI_HEADER_TYPE_NORMAL 0 135 #define PCI_HEADER_TYPE_BRIDGE 1 136 #define PCI_HEADER_TYPE_CARDBUS 2 137 138 #define PCI_BIST 0x0f /* 8 bits */ 139 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 140 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 141 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 142 143 /* 144 * Base addresses specify locations in memory or I/O space. 145 * Decoded size can be determined by writing a value of 146 * 0xffffffff to the register, and reading it back. Only 147 * 1 bits are decoded. 148 */ 149 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 150 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 151 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 152 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 153 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 154 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 155 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 156 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 157 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 158 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 159 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 160 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M */ 161 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 162 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 163 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 164 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 165 /* bit 1 is reserved if address_space = 1 */ 166 167 /* Header type 0 (normal devices) */ 168 #define PCI_CARDBUS_CIS 0x28 169 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 170 #define PCI_SUBSYSTEM_ID 0x2e 171 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 172 #define PCI_ROM_ADDRESS_ENABLE 0x01 173 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 174 175 /* 0x34-0x3b are reserved */ 176 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 177 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 178 #define PCI_MIN_GNT 0x3e /* 8 bits */ 179 #define PCI_MAX_LAT 0x3f /* 8 bits */ 180 181 /* Header type 1 (PCI-to-PCI bridges) */ 182 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 183 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 184 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 185 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 186 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 187 #define PCI_IO_LIMIT 0x1d 188 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 189 #define PCI_IO_RANGE_TYPE_16 0x00 190 #define PCI_IO_RANGE_TYPE_32 0x01 191 #define PCI_IO_RANGE_MASK ~0x0f 192 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 193 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 194 #define PCI_MEMORY_LIMIT 0x22 195 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 196 #define PCI_MEMORY_RANGE_MASK ~0x0f 197 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 198 #define PCI_PREF_MEMORY_LIMIT 0x26 199 #define PCI_PREF_RANGE_TYPE_MASK 0x0f 200 #define PCI_PREF_RANGE_TYPE_32 0x00 201 #define PCI_PREF_RANGE_TYPE_64 0x01 202 #define PCI_PREF_RANGE_MASK ~0x0f 203 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 204 #define PCI_PREF_LIMIT_UPPER32 0x2c 205 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 206 #define PCI_IO_LIMIT_UPPER16 0x32 207 /* 0x34-0x3b is reserved */ 208 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 209 /* 0x3c-0x3d are same as for htype 0 */ 210 #define PCI_BRIDGE_CONTROL 0x3e 211 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 212 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 213 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 214 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 215 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 216 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 217 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 218 219 /* Header type 2 (CardBus bridges) */ 220 /* 0x14-0x15 reserved */ 221 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 222 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 223 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 224 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 225 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 226 #define PCI_CB_MEMORY_BASE_0 0x1c 227 #define PCI_CB_MEMORY_LIMIT_0 0x20 228 #define PCI_CB_MEMORY_BASE_1 0x24 229 #define PCI_CB_MEMORY_LIMIT_1 0x28 230 #define PCI_CB_IO_BASE_0 0x2c 231 #define PCI_CB_IO_BASE_0_HI 0x2e 232 #define PCI_CB_IO_LIMIT_0 0x30 233 #define PCI_CB_IO_LIMIT_0_HI 0x32 234 #define PCI_CB_IO_BASE_1 0x34 235 #define PCI_CB_IO_BASE_1_HI 0x36 236 #define PCI_CB_IO_LIMIT_1 0x38 237 #define PCI_CB_IO_LIMIT_1_HI 0x3a 238 #define PCI_CB_IO_RANGE_MASK ~0x03 239 /* 0x3c-0x3d are same as for htype 0 */ 240 #define PCI_CB_BRIDGE_CONTROL 0x3e 241 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 242 #define PCI_CB_BRIDGE_CTL_SERR 0x02 243 #define PCI_CB_BRIDGE_CTL_ISA 0x04 244 #define PCI_CB_BRIDGE_CTL_VGA 0x08 245 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 246 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 247 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 248 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 249 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 250 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 251 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 252 #define PCI_CB_SUBSYSTEM_ID 0x42 253 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 254 /* 0x48-0x7f reserved */ 255 256 /* Device classes and subclasses */ 257 258 #define PCI_CLASS_NOT_DEFINED 0x0000 259 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 260 261 #define PCI_BASE_CLASS_STORAGE 0x01 262 #define PCI_CLASS_STORAGE_SCSI 0x0100 263 #define PCI_CLASS_STORAGE_IDE 0x0101 264 #define PCI_CLASS_STORAGE_FLOPPY 0x0102 265 #define PCI_CLASS_STORAGE_IPI 0x0103 266 #define PCI_CLASS_STORAGE_RAID 0x0104 267 #define PCI_CLASS_STORAGE_OTHER 0x0180 268 269 #define PCI_BASE_CLASS_NETWORK 0x02 270 #define PCI_CLASS_NETWORK_ETHERNET 0x0200 271 #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 272 #define PCI_CLASS_NETWORK_FDDI 0x0202 273 #define PCI_CLASS_NETWORK_ATM 0x0203 274 #define PCI_CLASS_NETWORK_OTHER 0x0280 275 276 #define PCI_BASE_CLASS_DISPLAY 0x03 277 #define PCI_CLASS_DISPLAY_VGA 0x0300 278 #define PCI_CLASS_DISPLAY_XGA 0x0301 279 #define PCI_CLASS_DISPLAY_OTHER 0x0380 280 281 #define PCI_BASE_CLASS_MULTIMEDIA 0x04 282 #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 283 #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 284 #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 285 286 #define PCI_BASE_CLASS_MEMORY 0x05 287 #define PCI_CLASS_MEMORY_RAM 0x0500 288 #define PCI_CLASS_MEMORY_FLASH 0x0501 289 #define PCI_CLASS_MEMORY_OTHER 0x0580 290 291 #define PCI_BASE_CLASS_BRIDGE 0x06 292 #define PCI_CLASS_BRIDGE_HOST 0x0600 293 #define PCI_CLASS_BRIDGE_ISA 0x0601 294 #define PCI_CLASS_BRIDGE_EISA 0x0602 295 #define PCI_CLASS_BRIDGE_MC 0x0603 296 #define PCI_CLASS_BRIDGE_PCI 0x0604 297 #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 298 #define PCI_CLASS_BRIDGE_NUBUS 0x0606 299 #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 300 #define PCI_CLASS_BRIDGE_OTHER 0x0680 301 302 #define PCI_BASE_CLASS_COMMUNICATION 0x07 303 #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 304 #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 305 #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 306 307 #define PCI_BASE_CLASS_SYSTEM 0x08 308 #define PCI_CLASS_SYSTEM_PIC 0x0800 309 #define PCI_CLASS_SYSTEM_DMA 0x0801 310 #define PCI_CLASS_SYSTEM_TIMER 0x0802 311 #define PCI_CLASS_SYSTEM_RTC 0x0803 312 #define PCI_CLASS_SYSTEM_OTHER 0x0880 313 314 #define PCI_BASE_CLASS_INPUT 0x09 315 #define PCI_CLASS_INPUT_KEYBOARD 0x0900 316 #define PCI_CLASS_INPUT_PEN 0x0901 317 #define PCI_CLASS_INPUT_MOUSE 0x0902 318 #define PCI_CLASS_INPUT_OTHER 0x0980 319 320 #define PCI_BASE_CLASS_DOCKING 0x0a 321 #define PCI_CLASS_DOCKING_GENERIC 0x0a00 322 #define PCI_CLASS_DOCKING_OTHER 0x0a01 323 324 #define PCI_BASE_CLASS_PROCESSOR 0x0b 325 #define PCI_CLASS_PROCESSOR_386 0x0b00 326 #define PCI_CLASS_PROCESSOR_486 0x0b01 327 #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 328 #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 329 #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 330 #define PCI_CLASS_PROCESSOR_CO 0x0b40 331 332 #define PCI_BASE_CLASS_SERIAL 0x0c 333 #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 334 #define PCI_CLASS_SERIAL_ACCESS 0x0c01 335 #define PCI_CLASS_SERIAL_SSA 0x0c02 336 #define PCI_CLASS_SERIAL_USB 0x0c03 337 #define PCI_CLASS_SERIAL_FIBER 0x0c04 338 339 #define PCI_CLASS_OTHERS 0xff 340 341 342 /* 343 * The PCI interface treats multi-function devices as independent 344 * devices. The slot/function address of each device is encoded 345 * in a single byte as follows: 346 * 347 * 7:3 = slot 348 * 2:0 = function 349 * 350 * see pci_find_slot() 351 */ 352 #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 353 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 354 #define PCI_FUNC(devfn) ((devfn) & 0x07) 355 356 357 #pragma pack() 358 359 #endif /* LIBRARIES_OPENPCI_H */