1 #ifndef LIBRARIES_PCIX_H 2 #define LIBRARIES_PCIX_H 3 4 #include <utility/tagitem.h> 5 6 /* 7 * PCIGetBoardAttr() attributes 8 */ 9 10 #define PCIXTAG_Dummy (TAG_USER + 0x100000) 11 12 #define PCIXTAG_BUS (PCIXTAG_Dummy + 0) 13 #define PCIXTAG_BRIDGENAME (PCIXTAG_Dummy + 1) 14 #define PCIXTAG_DEV (PCIXTAG_Dummy + 2) 15 #define PCIXTAG_FUNCTION (PCIXTAG_Dummy + 3) 16 #define PCIXTAG_ROMADDRESS (PCIXTAG_Dummy + 4) 17 #define PCIXTAG_ROMSIZE (PCIXTAG_Dummy + 5) 18 #define PCIXTAG_BASEADDRESS0 (PCIXTAG_Dummy + 20) 19 #define PCIXTAG_BASEADDRESS1 (PCIXTAG_Dummy + 21) 20 #define PCIXTAG_BASEADDRESS2 (PCIXTAG_Dummy + 22) 21 #define PCIXTAG_BASEADDRESS3 (PCIXTAG_Dummy + 23) 22 #define PCIXTAG_BASEADDRESS4 (PCIXTAG_Dummy + 24) 23 #define PCIXTAG_BASEADDRESS5 (PCIXTAG_Dummy + 25) 24 #define PCIXTAG_BASESIZE0 (PCIXTAG_Dummy + 26) 25 #define PCIXTAG_BASESIZE1 (PCIXTAG_Dummy + 27) 26 #define PCIXTAG_BASESIZE2 (PCIXTAG_Dummy + 28) 27 #define PCIXTAG_BASESIZE3 (PCIXTAG_Dummy + 29) 28 #define PCIXTAG_BASESIZE4 (PCIXTAG_Dummy + 30) 29 #define PCIXTAG_BASESIZE5 (PCIXTAG_Dummy + 31) 30 31 /* 32 * PCIGetBusAttr() special attributes 33 */ 34 35 #define PCIXTAG_SLOTS (PCIXTAG_Dummy + 32) 36 #define PCIXTAG_IOBASE (PCIXTAG_Dummy + 33) 37 /* 38 * Normal Attribute 39 */ 40 #define PCIXTAG_OWNER (PCIXTAG_Dummy + 40) 41 42 /* 43 * PCI ConfigSpace offsets for the 44 * PCIReadConfigByte() 45 * PCIReadConfigWord() 46 * PCIReadConfigLong() 47 * PCIWriteConfigByte() 48 * PCIWriteConfigWord() 49 * PCIWriteConfigLong() 50 * functions 51 */ 52 53 #define PCIXCONFIG_VENDOR (0x0) 54 #define PCIXCONFIG_DEVICE (0x2) 55 #define PCIXCONFIG_COMMAND (0x4) 56 #define PCIXCONFIG_STATUS (0x6) 57 #define PCIXCONFIG_REVISION (0x8) 58 #define PCIXCONFIG_PROGINTERFACE (0x9) 59 #define PCIXCONFIG_SUBCLASS (0xa) 60 #define PCIXCONFIG_CLASS (0xb) 61 #define PCIXCONFIG_CACHELINESIZE (0xc) 62 #define PCIXCONFIG_LATENCYTIMER (0xd) 63 #define PCIXCONFIG_HEADERTYPE (0xe) 64 #define PCIXCONFIG_BIST (0xf) 65 #define PCIXCONFIG_BASE0 (0x10) 66 #define PCIXCONFIG_BASE1 (0x14) 67 #define PCIXCONFIG_BASE2 (0x18) 68 #define PCIXCONFIG_BASE3 (0x1c) 69 #define PCIXCONFIG_BASE4 (0x20) 70 #define PCIXCONFIG_BASE5 (0x24) 71 #define PCIXCONFIG_CARDBUSCIS (0x28) 72 #define PCIXCONFIG_SUBSYSTEMVENDORID (0x2c) 73 #define PCIXCONFIG_SUBSYSTEMID (0x2e) 74 #define PCIXCONFIG_ROMBASE (0x30) 75 #define PCIXCONFIG_CAPPTR (0x34) 76 #define PCIXCONFIG_RESERVED2 (0x38) 77 #define PCIXCONFIG_INTERRUPTLINE (0x3c) 78 #define PCIXCONFIG_INTERRUPTPIN (0x3d) 79 #define PCIXCONFIG_MINGNT (0x3e) 80 #define PCIXCONFIG_MAXLAT (0x3f) 81 82 83 /* 84 * PCIFindBoardTagList() attributes 85 * PCIFindBridgeTagList() attributes 86 * only PCIXFINDTAG_NAME 87 */ 88 89 #define PCIXFINDTAG_Dummy (TAG_USER + 0x100100) 90 #define PCIXFINDTAG_BUS (PCIXFINDTAG_Dummy + 0x1) 91 /* 92 * Only search in a specific Device Slot 93 */ 94 #define PCIXFINDTAG_DEV (PCIXFINDTAG_Dummy + 0x2) 95 /* 96 * Only search in a specific Function 97 */ 98 #define PCIXFINDTAG_FUNCTION (PCIXFINDTAG_Dummy + 0x3) 99 /* 100 * PCI Class 101 */ 102 #define PCIXFINDTAG_CLASS (PCIXFINDTAG_Dummy + 0x4) 103 /* 104 * PCI Vendor 105 */ 106 #define PCIXFINDTAG_VENDOR (PCIXFINDTAG_Dummy + 0x5) 107 /* 108 * PCI Device 109 */ 110 #define PCIXFINDTAG_DEVICE (PCIXFINDTAG_Dummy + 0x6) 111 /* 112 * Care for hidden functions. 113 * There are board with hidden functions, though 114 * they aren't marked multifunction. 115 */ 116 #define PCIXFINDTAG_SHOWHIDDEN (PCIXFINDTAG_Dummy + 0x7) 117 /* 118 * Name Search Tag 119 * Only used with PCIFindBusTagList() 120 */ 121 #define PCIXFINDTAG_NAME (PCIXFINDTAG_Dummy + 0x8) 122 /* 123 * Ignore already owned boards. 124 */ 125 #define PCIXFINDTAG_IGNOREOWNED (PCIXFINDTAG_Dummy + 0x9) 126 /* 127 * PCI SubClass 128 */ 129 #define PCIXFINDTAG_SUBCLASS (PCIXFINDTAG_Dummy + 0xa) 130 /* 131 * Class and SubClass combined 132 * for the the PCI_CLASS_ defines below 133 */ 134 #define PCIXFINDTAG_FULLCLASS (PCIXFINDTAG_Dummy + 0xc) 135 136 137 /* 138 * PCICreateIntObject() attributes 139 */ 140 #define PCIXINTTAG_Dummy (TAG_USER + 0x100200) 141 #define PCIXINTTAG_PRI (PCIXINTTAG_Dummy + 0x1) 142 /* 143 * MorphOS Tag to specify the code type 144 */ 145 #define PCIXINTTAG_MACHINE (PCIXINTTAG_Dummy + 0x2) 146 147 148 149 150 151 #define PCI_CLASS_NOT_DEFINED 0x0000 152 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 153 154 #define PCI_BASE_CLASS_STORAGE 0x01 155 #define PCI_CLASS_STORAGE_SCSI 0x0100 156 #define PCI_CLASS_STORAGE_IDE 0x0101 157 #define PCI_CLASS_STORAGE_FLOPPY 0x0102 158 #define PCI_CLASS_STORAGE_IPI 0x0103 159 #define PCI_CLASS_STORAGE_RAID 0x0104 160 #define PCI_CLASS_STORAGE_OTHER 0x0180 161 162 #define PCI_BASE_CLASS_NETWORK 0x02 163 #define PCI_CLASS_NETWORK_ETHERNET 0x0200 164 #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 165 #define PCI_CLASS_NETWORK_FDDI 0x0202 166 #define PCI_CLASS_NETWORK_ATM 0x0203 167 #define PCI_CLASS_NETWORK_OTHER 0x0280 168 169 #define PCI_BASE_CLASS_DISPLAY 0x03 170 #define PCI_CLASS_DISPLAY_VGA 0x0300 171 #define PCI_CLASS_DISPLAY_XGA 0x0301 172 #define PCI_CLASS_DISPLAY_OTHER 0x0380 173 174 #define PCI_BASE_CLASS_MULTIMEDIA 0x04 175 #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 176 #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 177 #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 178 179 #define PCI_BASE_CLASS_MEMORY 0x05 180 #define PCI_CLASS_MEMORY_RAM 0x0500 181 #define PCI_CLASS_MEMORY_FLASH 0x0501 182 #define PCI_CLASS_MEMORY_OTHER 0x0580 183 184 #define PCI_BASE_CLASS_BRIDGE 0x06 185 #define PCI_CLASS_BRIDGE_HOST 0x0600 186 #define PCI_CLASS_BRIDGE_ISA 0x0601 187 #define PCI_CLASS_BRIDGE_EISA 0x0602 188 #define PCI_CLASS_BRIDGE_MC 0x0603 189 #define PCI_CLASS_BRIDGE_PCI 0x0604 190 #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 191 #define PCI_CLASS_BRIDGE_NUBUS 0x0606 192 #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 193 #define PCI_CLASS_BRIDGE_OTHER 0x0680 194 195 196 #define PCI_BASE_CLASS_COMMUNICATION 0x07 197 #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 198 #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 199 #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 200 201 #define PCI_BASE_CLASS_SYSTEM 0x08 202 #define PCI_CLASS_SYSTEM_PIC 0x0800 203 #define PCI_CLASS_SYSTEM_DMA 0x0801 204 #define PCI_CLASS_SYSTEM_TIMER 0x0802 205 #define PCI_CLASS_SYSTEM_RTC 0x0803 206 #define PCI_CLASS_SYSTEM_OTHER 0x0880 207 208 #define PCI_BASE_CLASS_INPUT 0x09 209 #define PCI_CLASS_INPUT_KEYBOARD 0x0900 210 #define PCI_CLASS_INPUT_PEN 0x0901 211 #define PCI_CLASS_INPUT_MOUSE 0x0902 212 #define PCI_CLASS_INPUT_OTHER 0x0980 213 214 #define PCI_BASE_CLASS_DOCKING 0x0a 215 #define PCI_CLASS_DOCKING_GENERIC 0x0a00 216 #define PCI_CLASS_DOCKING_OTHER 0x0a01 217 218 #define PCI_BASE_CLASS_PROCESSOR 0x0b 219 #define PCI_CLASS_PROCESSOR_386 0x0b00 220 #define PCI_CLASS_PROCESSOR_486 0x0b01 221 #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 222 #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 223 #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 224 #define PCI_CLASS_PROCESSOR_CO 0x0b40 225 226 #define PCI_BASE_CLASS_SERIAL 0x0c 227 #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 228 #define PCI_CLASS_SERIAL_ACCESS 0x0c01 229 #define PCI_CLASS_SERIAL_SSA 0x0c02 230 #define PCI_CLASS_SERIAL_USB 0x0c03 231 #define PCI_CLASS_SERIAL_FIBER 0x0c04 232 233 #define PCI_CLASS_OTHERS 0xff 234 235 236 237 /* Disconnect Device 238 */ 239 #define PCI_COMMAND_DISCONNECT 0x0 240 241 /* Enable response in I/O space 242 */ 243 #define PCI_COMMANDF_IO 0x1 244 245 /* Enable response in Memory space 246 */ 247 #define PCI_COMMANDF_MEMORY 0x2 248 249 /* Enable bus mastering 250 */ 251 #define PCI_COMMANDF_MASTER 0x4 252 253 /* Enable response to special cycles 254 */ 255 #define PCI_COMMANDF_SPECIAL 0x8 256 257 /* Use memory write and invalidate 258 */ 259 #define PCI_COMMANDF_INVALIDATE 0x10 260 261 /* Enable palette snooping 262 */ 263 #define PCI_COMMANDF_VGA_PALETTE 0x20 264 265 /* Enable parity checking 266 */ 267 #define PCI_COMMANDF_PARITY 0x40 268 269 /* Enable address/data stepping 270 */ 271 #define PCI_COMMANDF_WAIT 0x80 272 273 /* Enable SERR Driver 274 * PCI_COMMANDF_SERR AND PCI_COMMANDF_PARITY 275 * must be set to report parity errors 276 */ 277 #define PCI_COMMANDF_SERR 0x100 278 279 /* Enable back-to-back writes 280 */ 281 #define PCI_COMMANDF_FAST_BACK 0x200 282 283 284 285 286 /* Capability..PCI 2.2 287 */ 288 #define PCI_STATUSF_CAP_LIST 0x10 289 /* Support 66 Mhz PCI 2.1 bus 290 */ 291 #define PCI_STATUSF_66MHZ 0x20 292 /* Support User Definable Features 293 */ 294 #define PCI_STATUSF_UDF 0x40 295 296 /* Accept fast-back to back 297 */ 298 #define PCI_STATUSF_FAST_BACK 0x80 299 300 /* Detected parity error 301 */ 302 #define PCI_STATUSF_PARITY 0x100 303 304 /* DEVSEL timing 305 */ 306 #define PCI_STATUSF_DEVSEL_MASK 0x600 307 #define PCI_STATUSF_DEVSEL_FAST 0x000 308 #define PCI_STATUSF_DEVSEL_MEDIUM 0x200 309 #define PCI_STATUSF_DEVSEL_SLOW 0x400 310 311 /* Set on target abort 312 */ 313 #define PCI_STATUSF_SIG_TARGET_ABORT 0x800 314 /* Master ack of 315 */ 316 #define PCI_STATUSF_REC_TARGET_ABORT 0x1000 317 /* Set on master abort 318 */ 319 #define PCI_STATUSF_REC_MASTER_ABORT 0x2000 320 321 /* Set when we drive SERR 322 */ 323 #define PCI_STATUSF_SIG_SYSTEM_ERROR 0x4000 324 /* Set on parity error 325 */ 326 #define PCI_STATUSF_DETECTED_PARITY 0x8000 327 328 #endif /* LIBRARIES_PCI_H */