1 #ifndef POWERUP_PPCLIB_MEMORY_H
    2 #define POWERUP_PPCLIB_MEMORY_H
    3 
    4 
    5 /* Allocate Memory with the Pages marked as writethrough
    6    on the PPC. This means the whole memory size which is allocated
    7    is aligned to 4k pages. So you better use Pools.
    8  */
    9    
   10 #define MEMF_WRITETHROUGHPPC	(1L<<22)	/* WriteThrough Pools */
   11 
   12 /* Allocate Memory with the Pages marked as writethrough
   13    on the PPC. This means the whole memory size which is allocated
   14    is aligned to 4k pages. So you better use Pools.
   15    (V46)
   16  */
   17    
   18 #define MEMF_WRITETHROUGHM68K	(1L<<23)	/* WriteThrough Pools */
   19 
   20 /* Allocate Memory with the Pages marked as NOCACHE (not synchronisized)
   21    on the PPC. This means the whole memory size which is allocated
   22    is aligned to 4k pages. So you better use Pools.
   23    (V46)
   24  */
   25    
   26 #define MEMF_NOCACHEPPC		(1L<<24)	/* NoCache Pools */
   27 
   28 /* Allocate Memory with the Pages marked as NOCACHE
   29    on the M68k. This means the whole memory size which is allocated
   30    is aligned to 4k pages. So you better use Pools.
   31    (V46)
   32  */
   33 #define MEMF_NOCACHEM68K	(1L<<25)	/* NoCache Pools */
   34 
   35 /* Allocate Memory with the Pages marked as NOCACHE GUARD(synchronisized)
   36    on the PPC. This means the whole memory size which is allocated
   37    is aligned to 4k pages. So you better use Pools.
   38    (V46)
   39  */
   40    
   41 #define MEMF_NOCACHESYNCPPC	(1L<<29)	/* NoCache synchronized Pools */
   42 
   43 /* Allocate Memory with the Pages marked as NOCACHE synchronisized
   44    on the M68k. This means the whole memory size which is allocated
   45    is aligned to 4k pages. So you better use Pools.
   46  */
   47 #define MEMF_NOCACHESYNCM68K	(1L<<30)	/* NoCache synchronized Pools */
   48 
   49 
   50 
   51 #define MEMF_PPCMASK		(MEMF_NOCACHEPPC |		\
   52                                  MEMF_NOCACHEM68K |		\
   53                                  MEMF_NOCACHESYNCPPC |		\
   54                                  MEMF_NOCACHESYNCM68K |		\
   55                                  MEMF_WRITETHROUGHPPC |		\
   56                                  MEMF_WRITETHROUGHM68K)
   57 
   58 #endif